Semiconductor device including control switches to reduce pin capacitance
US11177239B2 · kind B2 · utility
1Cited by
2References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2018 |
| Grant date | Nov 16, 2021 |
| Priority date | — |
| Expiry date | Apr 19, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device including control switches enabling a semiconductor die in a stack of semiconductor die to send or receive a signal, while electrically isolating the remaining die in the die stack. Parasitic pin cap is reduced or avoided by electrically isolating the non-enabled semiconductor die in the die stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.