Patent · US Active

Semiconductor device with top die positioned to reduce die cracking

US11177241B2 · kind B2 · utility

0Cited by

10References

20Claims

0Family size

Assignee

Western Digital Technologies, Inc. · US

Inventors

Junrong Yan · Shanghai, CN
Jianming Zhang · Campbell, US
Min Zhao · Shanghai, CN
Kailei Zhang · Shanghai, CN
Chee Keong Chin · Shanghai, CN
Kim Lee Bock · Shanghai, CN

Key dates

Filing date	Mar 10, 2020
Grant date	Nov 16, 2021
Priority date	—
Expiry date	Apr 1, 2040

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/1815
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A semiconductor device is disclosed including a die stack including a number of dies aligned with each other with respect to an axis, and a top die that is offset along the axis the to prevent die cracking.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.