Apparatus for enhancing prefetch access in memory module
US11183231B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2020 |
| Grant date | Nov 23, 2021 |
| Priority date | — |
| Expiry date | Jun 17, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/108
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for enhancing prefetch access in a memory module may include a memory chip. The memory chip includes a memory cell array, a plurality of bit lines and a plurality of word lines, a plurality of BLSAs, and a plurality of main data lines. The memory cell array may be arranged to store data, and the plurality of bit lines and the plurality of word lines may be arranged to perform access control of the memory cell array. The plurality of BLSAs may sense a plurality of bit-line signals restored from the plurality of memory cells and convert the plurality of bit-line signals into a plurality of amplified signals, respectively. The main data lines may directly output the amplified signals, through selection of CSLs of the BLSAs on the memory chip, to a secondary semiconductor chip, for performing further processing of the memory module, thereby enhancing the prefetch access.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.