Apparatuses and methods for repairing defective memory cells based on a specified error rate for certain memory cells
US11183266B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2019 |
| Grant date | Nov 23, 2021 |
| Priority date | — |
| Expiry date | Nov 24, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L61/2575
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, apparatuses, and systems for repairing defective memory cells in regions of a memory array associated with high or low priority levels are disclosed. A repair address generator may be configured to generate a memory address map for repair (e.g., blowing fuses at a fuse circuit), depending on whether certain applications may operate at a high priority level indicative of a low bit error rate or a low priority level indicative of a higher bit error rate. For example, a specified error rate associated with a low priority level may correspond to a threshold error rate for certain applications, such as a neural network application that stores trained weights. Such neural network applications may access trained weights being partially stored in defective memory cells, with the least significant bits of such trained weights being stored in defective memory cells that are not repaired according to the memory address map.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.