Multilevel template assisted wafer bonding
US11183492B2 · kind B2 · utility
2Cited by
43References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2018 |
| Grant date | Nov 23, 2021 |
| Priority date | — |
| Expiry date | Jun 8, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/018
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Fabricating a multilevel composite semiconductor structure includes providing a first substrate comprising a first material; dicing a second substrate to provide a plurality of dies; mounting the plurality of dies on a third substrate; joining the first substrate and the third substrate to form a composite structure; and joining a fourth substrate and the composite structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.