Unified functional coverage and synthesis flow for formal verification and emulation
US11188695B2 · kind B2 · utility
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17Claims
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Key dates
| Filing date | Aug 8, 2018 |
| Grant date | Nov 30, 2021 |
| Priority date | — |
| Expiry date | Mar 31, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Synthesis of functional coverage (e.g., covergroups) is optimized for hardware emulation. The optimization may reduce the number of logic gates used to implement the hardware emulator circuits or reduce the computer resources used to synthesize the hardware emulator circuits. The optimization may also prevent the synthesis of unnecessary circuits. In another aspect, the optimization may result in a representation that may be used both to synthesize hardware emulation circuits and as part of formal verification. This may result in a model that can be used for formal verification, hardware emulation, and software simulation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.