Processing array device that performs one cycle full adder operation and bit line read/write logic features
US11194548B2 · kind B2 · utility
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284References
12Claims
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Key dates
| Filing date | Oct 6, 2020 |
| Grant date | Dec 7, 2021 |
| Priority date | — |
| Expiry date | Oct 6, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/21
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing array that performs one cycle full adder operations. The processing array may have different bit line read/write logic that permits different operations to be performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.