Patent · US Active

False path timing exception handler circuit

US11194944B2 · kind B2 · utility

0Cited by

9References

2Claims

0Family size

Assignee

TEXAS INSTRUMENTS INCORPORATED · US

Inventors

Wilson Pradeep · Savanuru, IN
Prakash Narayanan · Bengaluru, IN
Saket Jalan · Bengaluru, IN

Key dates

Filing date	Aug 11, 2020
Grant date	Dec 7, 2021
Priority date	—
Expiry date	Aug 11, 2040

Classification

Technology area (CPC H)Electricity
CPC primaryH10D62/17
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method that includes disabling circuit paths in a circuit under test during transition fault testing (TFT) of valid timing paths of the circuit under test. The method then tests the circuit paths at slower clock speeds than the clock speed of the valid timing paths during TFT of the circuit paths. Finally, the method tests the circuit paths and the valid timing paths to facilitate testing of the circuit under test.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.