Method of manufacturing a semiconductor device including the horizontal channel FET and the vertical channel FET

US11201093B2 · kind B2 · utility

Assignee

• IMEC VZW · BE

Inventors

• Anabela Veloso · Leuven, BE
• Trong Huynh Bao · Leuven, BE
• Julien Ryckaert · Schaerbeek - Schaarbeek, BE
• Raf Appeltans · Haasrode, BE

Key dates

• Filing date: Mar 31, 2020
• Grant date: Dec 14, 2021
• Expiry date: Jun 6, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6728
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

A method of fabricating a semiconductor device is disclosed. In one aspect, the method includes forming, in a vertical channel field-effect transistor (FET) device region, a vertical channel FET device including a first semiconductor structure including a lower source/drain portion, an upper source/drain portion, a first channel portion extending vertically and intermediate the source/drain portions and a gate structure extending along the channel portion and, in a horizontal channel FET device region, a horizontal channel FET device comprising a second semiconductor structure including a first source/drain portion, a second source/drain portion, a second channel portion extending horizontally and intermediate the source/drain portions, and a gate structure extending across the channel portion.