Method and apparatus for scheduling thread order to improve cache efficiency
US11204801B2 · kind B2 · utility
0Cited by
0References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2019 |
| Grant date | Dec 21, 2021 |
| Priority date | — |
| Expiry date | Feb 14, 2040 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for scheduling thread order to improve cache efficiency are disclosed. In one embodiment, a graphics processor includes processing resources and schedule and dispatch logic to schedule and dispatch threads to the processing resources. The schedule and dispatch logic is configured to receive threads, to schedule and dispatch the threads based on a forward thread dispatch having a forward thread order, and to determine whether to disable a reversing of a thread order upon completion of at least a portion of the forward thread dispatch including a completion or ending of a draw call or a dispatch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.