Memory system with low-latency read recovery and method of operating the memory system
US11204839B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2020 |
| Grant date | Dec 21, 2021 |
| Priority date | — |
| Expiry date | Feb 20, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/85
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Multiple memory systems with respective decoders employ a low latency implementation of a read recovery level feature in decoding data. The decoding comprises receiving from a host a read request for decoding read data at a first recovery level by a first memory system, a first decoder of the first memory system being set at a second recovery level with a corresponding maximum iteration number when the read request is received by the first memory system; and operating the first decoder, after a set time elapses, to decode the read data at the second recovery level. A second decoder of a second memory system is set at the first recovery level for at least part of the time during which the first decoder operates to decode the read data at the second recovery level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.