Patent · US Active

Ferroelectric memory and logic cell and operation method

US11205467B2 · kind B2 · utility

3Cited by

8References

23Claims

0Family size

Assignee

NAMLAB GGMBH · DE

Inventors

Stefan Slesazeck · Dresden, DE
Milan Pesic · Berlin, DE

Key dates

Filing date	Feb 5, 2020
Grant date	Dec 21, 2021
Priority date	—
Expiry date	Jun 16, 2040

Classification

Technology area (CPC G)Physics
CPC primaryG06N3/065
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

One example provides a memory cell including a node, and a layer stack including a first electrode, a second electrode connected to the node, and a polarizable material layer disposed between the first and second electrodes and having at least two polarization states. A first transistor includes a source, a drain, and a gate terminal, with the gate terminal connected to the node. A selector element includes at least a first terminal and a second terminal, with the second terminal connected to the node.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.