Read data processing circuits and methods associated with computational memory cells
US11205476B1 · kind B1 · utility
3Cited by
282References
24Claims
0Family size
Assignee
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Key dates
| Filing date | May 28, 2020 |
| Grant date | Dec 21, 2021 |
| Priority date | — |
| Expiry date | May 28, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A read register is provided that captures and stores the read result on a read bit line connected to a set of computational memory cells. The read register may be implemented in the set of computational memory cell to enable the logical XOR, logical AND, and/or logical OR accumulation of read results in the read register. The set of computational memory cells with the read register provides a mechanism for performing complex logical functions across multiple computational memory cells connected to the same read bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.