Semiconductor device and method
US11205597B2 · kind B2 · utility
3Cited by
1References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2019 |
| Grant date | Dec 21, 2021 |
| Priority date | — |
| Expiry date | Jul 1, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0188
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes forming a first fin extending from a substrate, forming a first gate stack over and along sidewalls of the first fin, forming a first spacer along a sidewall of the first gate stack, the first spacer including a first composition of silicon oxycarbide, forming a second spacer along a sidewall of the first spacer, the second spacer including a second composition of silicon oxycarbide, forming a third spacer along a sidewall of the second spacer, the third spacer including silicon nitride, and forming a first epitaxial source/drain region in the first fin and adjacent the third spacer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.