Interconnect structures of three-dimensional memory devices
US11205659B2 · kind B2 · utility
5Cited by
3References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2019 |
| Grant date | Dec 21, 2021 |
| Priority date | — |
| Expiry date | Nov 13, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack, a channel structure, and a slit structure. The memory stack includes interleaved conductive layers and dielectric layers above the substrate. The channel structure extends vertically through the memory stack. The slit structure extends vertically through the memory stack. An upper end of the slit structure is above an upper end of the channel structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.