Self-aligned nanowire
US11205715B2 · kind B2 · utility
1Cited by
1References
19Claims
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Key dates
| Filing date | Aug 21, 2017 |
| Grant date | Dec 21, 2021 |
| Priority date | — |
| Expiry date | Aug 21, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/018
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method comprising: forming a substrate; forming a first nanowire over the substrate; forming a second nanowire over the substrate; forming a gate over a portion of the first and second nanowires; implanting a dopant such that a region between the first and second nanowires under the gate does not receive the dopant while a region between the first and second nanowires away from the gate receives the dopant, wherein the dopant amorphize a material of the region between the first and second nanowires away from the gate; and isotopically etching of the region between the first and second nanowires away from the gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.