Inventor · Portland, OR, US

Bruce Beattie

22Patents
6h-index
27Co-inventors
69Inventor score

Filing activity: Feb 3, 1988 → Jan 11, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US6124171A Method of forming gate oxide having dual thickness by oxidation process Emerging Cross-Sectional Technologies 51 Expired
US6087236A Integrated circuit with multiple gate dielectric structures Electricity 43 Expired
US6465358B1 Post etch clean sequence for making a semiconductor device Emerging Cross-Sectional Technologies 29 Expired
US5898968A Accessory for cleaning golf club heads and golf balls Emerging Cross-Sectional Technologies 27 Expired
US6597046B1 Integrated circuit with multiple gate dielectric structures Electricity 16 Expired
US9041106B2 Three-dimensional germanium-based semiconductor devices formed on globally or locally isolated substrates Electricity 8 Active
US4909185A Cantilever and cold zone assembly for loading and unloading an oven Emerging Cross-Sectional Technologies 4 Expired
US11342411B2 Cavity spacer for nanowire transistors Electricity 4 Active
US11404578B2 Dielectric isolation layer between a nanowire transistor and a substrate Electricity 2 Active
US9472399B2 Three-dimensional germanium-based semiconductor devices formed on globally or locally isolated substrates Electricity 2 Active
US11205715B2 Self-aligned nanowire Electricity 1 Active
US11894368B2 Gate-all-around integrated circuit structures fabricated using alternate etch selective material Electricity 1 Active
US11869891B2 Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process Electricity 1 Active
US11929396B2 Cavity spacer for nanowire transistors Electricity 1 Active
US11901458B2 Dielectric isolation layer between a nanowire transistor and a substrate Electricity 0 Active
US12302632B2 Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process Electricity 0 Active
US11069795B2 Transistors with channel and sub-channel regions with distinct compositions and dimensions Electricity 0 Active
US11869973B2 Nanowire transistor structure and method of shaping Electricity 0 Active
US11715787B2 Self-aligned nanowire Electricity 0 Active
US12349394B2 Dielectric isolation layer between a nanowire transistor and a substrate Electricity 0 Active
US11276691B2 Gate-all-around integrated circuit structures having self-aligned source or drain undercut for varied widths Electricity 0 Active
US12328905B2 Cavity spacer for nanowire transistors Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.