Stressing integrated circuits using a radiation source
US11209479B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2019 |
| Grant date | Dec 28, 2021 |
| Priority date | — |
| Expiry date | Jul 15, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/20
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Various aspects of the present invention disclose a test device that includes a retaining element retaining one or more nuclear radiation sources for performing a nuclear radiation stress test of data storage structures of integrated circuits on a wafer in a wafer prober. The retaining element includes one or more apertures for applying nuclear radiation from the one or more nuclear radiation sources to the data storage structures. The retaining element is configured for controlling the nuclear radiation applied via the one or more apertures. The controlling includes a varying of relative positions of the one or more nuclear radiation sources and the one or more apertures. Additional aspects of the present invention disclose a testing method, computer program product, and computer system for performing the nuclear radiation stress test. In an example aspect, embodiments of the present invention disclose a test device for a wafer prober.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.