Semiconductor device including trench isolation layer and method of forming the same
US11211284B2 · kind B2 · utility
0Cited by
2References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 3, 2020 |
| Grant date | Dec 28, 2021 |
| Priority date | — |
| Expiry date | Feb 3, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76232
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a plurality of patterns defined between a plurality of trenches and disposed on a substrate. A leaning control layer is disposed on sidewalls and bottoms of the plurality of trenches. A gap-fill insulating layer is disposed on the leaning control layer. At least one of the plurality of trenches has a different depth from one of the plurality of trenches adjacent thereto.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.