Airgap formation processes

US11211286B2 · kind B2 · utility

Assignee

• Applied Materials, Inc. · US

Inventors

• Ashish Pal · Hayward, US
• Gaurav Thareja · Santa Clara, US
• Sankuei Lin · Los Gatos, US
• Ching-Mei Hsu · Stanford, US
• Nitin K. Ingle · San Jose, US
• Ajay Bhatnagar · Santa Clara, US
• Anchuan Wang · San Jose, US

Key dates

• Filing date: Feb 15, 2019
• Grant date: Dec 28, 2021
• Expiry date: Feb 15, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/151
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Processing methods may be performed to form an airgap spacer on a semiconductor substrate. The methods may include forming a spacer structure including a first material and a second material different from the first material. The methods may include forming a source/drain structure. The source/drain structure may be offset from the second material of the spacer structure by at least one other material. The methods may also include etching the second material from the spacer structure to form the airgap. The source/drain structure may be unexposed to etchant materials during the etching.