Memory devices based on ferroelectric field effect transistors
US11211404B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 9, 2019 |
| Grant date | Dec 28, 2021 |
| Priority date | — |
| Expiry date | Sep 9, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B51/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The disclosed technology is generally directed to semiconductor integrated circuit devices and more particularly to a three-transistor random access memory (3T RAM) device, and a method of fabricating and operating the same. In one aspect, a 3T RAM cell includes a ferroelectric-based field effect transistor (FeFET) having a first gate connected as a storage node and a second transistor connected between the FeFET and a read bit line having a second gate connected to a read word line. The 3T RAM cell also includes a third transistor connected between the storage node and a write bit line having a third gate connected to a write word line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.