Data buffering operation of three-dimensional memory device with static random-access memory
US11221793B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 16, 2019 |
| Grant date | Jan 11, 2022 |
| Priority date | — |
| Expiry date | Apr 23, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2245
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of three-dimensional (3D) memory devices with a 3D NAND memory array having a plurality of pages and an on-die data buffer coupled to the memory array on a same chip and configured to buffer a plurality of batches of program data between a host and the memory array. The on-die data buffer may include SRAM cells. The 3D memory device also includes a controller coupled to the on-die data buffer on the same chip. The controller may be configured to receive control instructions for performing a first pass program and a second pass program on memory cells in a page. The controller may also be configured to buffer, in the on-die data buffer, first program data for a first pass program and second program data for a second pass program from a host and retrieve the first program data from the on-die data buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.