Write/read turn techniques based on latency tolerance
US11221798B2 · kind B2 · utility
1Cited by
6References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2020 |
| Grant date | Jan 11, 2022 |
| Priority date | — |
| Expiry date | Jun 10, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0673
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques relating to arbitration in a memory controller are disclosed. In some embodiments, the memory controller is configured to transition between read turns and writes turn according to a turn schedule. In some embodiments, the memory controller also receives reports from circuitry requesting memory transactions and determines a current latency tolerance value based on the reports. In some embodiments, the memory controller is configured to switch from a write turn to a read turn prior to a scheduled switch based on the current latency tolerance meeting a threshold value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.