Method of sequentially biasing bias lines in memory device for program disturbance reduction and memory device utilizing same

US11222674B2 · kind B2 · utility

Assignee

• YANGTZE MEMORY TECHNOLOGIES CO., LTD. · CN

Inventors

• Shan Li · 红钢城街道, CN
• Kaikai You · 红钢城街道, CN
• Ying Cui · 红钢城街道, CN
• Jianquan Jia · 红钢城街道, CN
• Kaiwei Li · 红钢城街道, CN
• An Zhang · Kunshan, CN

Key dates

• Filing date: Jan 13, 2020
• Grant date: Jan 11, 2022
• Expiry date: Jan 13, 2040

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C16/3427
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A memory device includes a top select cell, a top dummy cell and a string of memory cells. The top select cell has a first terminal coupled to a bit line and a control terminal coupled to a top select line. The top dummy cell has a control terminal coupled to a top dummy word line. The string of memory cells has control terminals coupled to respective word lines. A method operating the memory device includes prior to a program operation, applying a pre-pulse voltage to the top dummy word line, the top select line and the bit line while applying a low voltage to the word lines, and then sequentially applying the low voltage to the top dummy word line, the top select line and the bit line while applying the low voltage to the word lines.