Socket design for a memory device
US11222695B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2019 |
| Grant date | Jan 11, 2022 |
| Priority date | — |
| Expiry date | Nov 15, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8825
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices supporting a socket design for a memory device are described. A die may include one or more memory arrays, which each may include any number of word lines and any number of bit lines. The word lines and the bit lines may be oriented in different directions, and memory cells may be located at the intersections of word lines and bit lines. Sockets may couple the word lines and bit lines to associated drivers, and the sockets may be located such that memory cells farther from a corresponding word line socket are nearer a corresponding bit line socket, and vice versa. For example, sockets may be disposed in rows or regions that are parallel to one another, and which may be non-orthogonal to the corresponding word lines and bit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.