Via structures for use in semiconductor devices
US11222844B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2020 |
| Grant date | Jan 11, 2022 |
| Priority date | — |
| Expiry date | Jun 11, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B53/30
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. The present disclosure provides a semiconductor device including a first device region and a second device region. The first device region includes a first metal layer, a first via structure over the first metal layer, a second via structure over the first via structure, and a second metal layer over the second via structure. The first via structure and the second via structure electrically couple the second metal layer to the first metal layer. The second device region includes a third metal layer, a contact structure over the third metal layer, a memory cell structure over the contact structure, and a fourth metal layer over the memory cell structure. The first via structure and the contact structure are made of the same material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.