Static random access memory (SRAM) bit cells employing asymmetric width read and write word lines, and related methods

US11222846B1 · kind B1 · utility

Assignee

• QUALCOMM Incorporated · US

Inventors

• Sunil Sharma · Salt Lake City, US
• Rahul Biradar · Kalaburagi, IN
• Sonia Ghosh · San Diego, US

Key dates

• Filing date: Aug 25, 2020
• Grant date: Jan 11, 2022
• Expiry date: Aug 25, 2040

Classification

• Technology area (CPC —): General

Abstract

Static random access memory (SRAM) bit cells employing asymmetric width read and write word lines (WWL) for reduced memory write latency and improved memory write access performance, and related fabrication methods are disclosed. In exemplary aspects, the SRAM bit cell employs an increased width write word line based on a circuit cell layout area savings achieved by employing a reduced width read word line. Increasing the width of the write word line can reduce the resistance of the write word line and decrease memory write latency to the SRAM bit cell as a result. In certain exemplary aspects, the metal line pitch and minimum distance between metal lines of the SRAM bit cell can be maintained for maintaining fabrication compatibility with existing fabrication processes with decreasing the resistance of the write word line of the SRAM bit cell.