System-level testing apparatus and system-level testing system
US11226362B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2020 |
| Grant date | Jan 18, 2022 |
| Priority date | — |
| Expiry date | Nov 30, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2886
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system-level testing apparatus and a system-level testing system are provided. The system-level testing apparatus includes an apparatus body, a chip carrying device, and a control device. A holding structure in the apparatus body is configured to hold a system circuit board. The chip carrying device includes a carrying circuit board, and a plurality of electrical connection sockets and a plurality of connection structures are disposed on the carrying circuit board. The electrical connection structures are electrically connected to the connection structures. When the electrical connection sockets carry a plurality of chips under test, the carrying circuit board is disposed on the system circuit board, and the connection structures are connected to a plurality of system connection structures of the system circuit board, the control device can transmit a test signal to perform a system-level test operation to the system circuit board and the chips under test.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.