Sidewall protection layer formation for substrate processing
US11232954B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 16, 2020 |
| Grant date | Jan 25, 2022 |
| Priority date | — |
| Expiry date | Mar 16, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02238
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Substrate processing techniques are described in which an etch protection layer that is formed as part of an etch process forms in a self-limiting nature. Thus, over deposition effects are minimized, particularly in the corners of etched polygonal holes. In one embodiment, the layer being etched contains silicon and the protective layer comprises a silicon oxide (SixOy). The process may include the use of a cyclical series of etch and protective layer formation steps. In the case of a silicon oxide based protective layer, a thin protective layer of silicon oxide may be formed in a limiting and controllable manner due to the nature of the oxygen atom interaction with silicon and newly formed silicon oxide protective layers. In this manner, a polygonal hole may be formed without detrimental over deposition of a protective layer in corners of the hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.