Memory devices and methods of forming memory devices
US11233195B2 · kind B2 · utility
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1References
19Claims
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Assignee
Inventors
Key dates
| Filing date | Jun 5, 2020 |
| Grant date | Jan 25, 2022 |
| Priority date | — |
| Expiry date | Aug 8, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
Abstract
A memory device may be provided, including a base layer; an insulating layer arranged over the base layer, where the insulating layer may include a recess having opposing side walls; a first electrode arranged along the opposing side walls of the recess; a switching element arranged along the first electrode; a second electrode arranged along the switching element; and a capping layer arranged over the recess, where the capping layer may at least partially overlap the first electrode, the switching element and the second electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.