Series of parallel sensing operations for multi-level cells
US11238906B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2020 |
| Grant date | Feb 1, 2022 |
| Priority date | — |
| Expiry date | Jun 15, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5634
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed herein are related to a circuit and a method of reading or sensing multiple bits of data stored by a multi-level cell. In one aspect, a first reference circuit is selected from a first set of reference circuits, and a second reference circuit is selected from a second set of reference circuits. Based at least in part on the first reference circuit and the second reference circuit, one or more bits of multiple bits of data stored by a multi-level cell can be determined. According to the determined one or more bits, a third reference circuit from the first set of reference circuits and a fourth reference circuit from the second set of reference circuits can be selected. Based at least in part on the third reference circuit and the fourth reference circuit, additional one or more bits of the multiple bits of data stored by the multi-level cell can be determined.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.