Method for manufacturing a pressure sensitive field effect transistor including a membrane structure

US11239375B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Vladislav Komenko · Dresden, DE
• Heiko Froehlich · Radebeul, DE
• Thoralf Kautzsch · Dresden, DE
• Andrey Kravchenko · Dresden, DE
• Bernhard Winkler · Birkenfeld, DE

Key dates

• Filing date: Sep 27, 2019
• Grant date: Feb 1, 2022
• Expiry date: Nov 6, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/126
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for manufacturing a pressure sensitive transistor includes forming a channel region between first and second contact regions in a semiconductor substrate, forming a first isolation layer on a surface of the semiconductor substrate, forming a sacrificial structure on the first isolation layer and above the channel region, forming a semiconductor layer on the sacrificial structure and on the first isolation layer, wherein the semiconductor layer covers the sacrificial structure, removing the sacrificial structure for providing a cavity between the substrate and the semiconductor layer, wherein the semiconductor layer forms a membrane structure and forms a control electrode of the pressure sensitive transistor, forming a second isolation layer on the membrane structure and on the exposed portion of the surface of the semiconductor substrate, and forming contacting structures for the first contact region, the second contact region and the membrane structure of the pressure sensitive transistor.