Patent · US Active

Identifying translation errors

US11243864B2 · kind B2 · utility

0Cited by

6References

18Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Bryant Cockcroft · Austin, US
John A. Schumann · Austin, US
Debapriya Chatterjee · Austin, US
Larry Scott Leitner · Austin, US
Kevin Barnett · Austin, US
Karen Yokum · Austin, US

Key dates

Filing date	Sep 17, 2019
Grant date	Feb 8, 2022
Priority date	—
Expiry date	Sep 17, 2039

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/151
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An instruction may be associated with a memory address. During execution of the instruction, the memory address may be translated to a next level memory address. The instruction may also be marked for address tracing. If the instruction is marked for address tracing, then during execution of the instruction, the memory address and the next level memory address may be recorded.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.