Non-volatile memory with multiplexer transistor regulator circuit
US11250898B2 · kind B2 · utility
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18Claims
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Key dates
| Filing date | Apr 10, 2020 |
| Grant date | Feb 15, 2022 |
| Priority date | — |
| Expiry date | Apr 10, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
As disclosed herein, a memory includes an array of resistive memory cells and a voltage regulator circuit that provides a regulated voltage based on a circuit with a replica resistive storage element. The regulated voltage is applied to a mux transistor of a multiplexer of a column decoder that is used to select a particular column line of a memory array from a set of column lines to provide the proper voltage to the memory cell during a write operation to the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.