Fabrication and use of through silicon vias on double sided interconnect device
US11251156B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2015 |
| Grant date | Feb 15, 2022 |
| Priority date | — |
| Expiry date | Dec 23, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An apparatus including a circuit structure including a device stratum; one or more electrically conductive interconnect levels on a first side of the device stratum and coupled to ones of the transistor devices; and a substrate including an electrically conductive through silicon via coupled to the one or more electrically conductive interconnect levels so that the one or more inter connect levels are between the through silicon via and the device stratum. A method including forming a plurality of transistor devices on a substrate, the plurality of transistor devices defining a device stratum; forming one or more interconnect levels on a first side of the device stratum; removing a portion of the substrate; and coupling a through silicon via to the one or more interconnect levels such that the one or more interconnect levels is disposed between the device stratum and the through silicon via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.