Carrier for a semiconductor structure
US11251265B2 · kind B2 · utility
2Cited by
3References
21Claims
0Family size
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Key dates
| Filing date | Feb 23, 2017 |
| Grant date | Feb 15, 2022 |
| Priority date | — |
| Expiry date | Sep 18, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8325
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A support for a semiconductor structure includes a charge-trapping layer on a base substrate. The charge-trapping layer consists of a polycrystalline main layer and, interposed in the main layer or between the main layer and the base substrate, at least one intermediate polycrystalline layer composed of a silicon and carbon alloy or carbon. The intermediate layer has a resistivity greater than 1000 ohm·cm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.