Self-aligned uniform bottom spacers for VTFETS
US11251287B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 2020 |
| Grant date | Feb 15, 2022 |
| Priority date | — |
| Expiry date | Apr 14, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/013
Abstract
Semiconductor devices and methods of forming the same include forming a bottom source/drain structure around a fin. A multi-layer bottom spacer is formed on the bottom source/drain structure, around the fin. Each layer of the multi-layer bottom spacer has a respective vertical height above the bottom source/drain structure, with a layer of the multi-layer bottom spacer that is farthest from the fin having a greater vertical height than a layer that is closest to the fin, to address parasitic capacitance from the bottom source/drain structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.