Patent · US Active

Instruction scheduling during execution in a processor

US11256511B2 · kind B2 · utility

0Cited by

7References

20Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Cedric Lichtenau · Stuttgart, DE
Stefan Payer · Stuttgart, DE
Kerstin Claudia Schelm · Stuttgart, DE
Anthony Saporito · Highland, US
Gregory W. Alexander · Pflugerville, US

Key dates

Filing date	May 20, 2019
Grant date	Feb 22, 2022
Priority date	—
Expiry date	Oct 25, 2039

Classification

Technology area (CPC G)Physics
CPC primaryG06F9/50
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method of performing instruction scheduling during execution in a processor includes receiving, at an execution unit of the processor, an initial assignment of an assigned execution resource among two or more execution resources to execute an operation. An instruction includes two or more operations. Based on determining that the assigned execution resource is not available, the method also includes determining, at the execution unit, whether another execution resource among the two or more execution resources is available to execute the operation. Based on determining that the other execution resource is available, the method further includes executing the operation with the other execution resource.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.