Dual spacer metal patterning
US11257673B2 · kind B2 · utility
0Cited by
14References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 19, 2019 |
| Grant date | Feb 22, 2022 |
| Priority date | — |
| Expiry date | Aug 19, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76852
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for patterning a metal layer includes depositing a hard mask layer on a metal layer, depositing a first patterned layer on the hard mask layer, forming a first set of sidewall spacers on sidewalls of features of the first patterned layer, forming a second set of sidewall spacers on sidewalls of the first set of sidewall spacers, removing the first set of sidewall spacers, and performing a reactive ion etching process to pattern portions of the metal layer exposed through the first patterned layer and the second set of sidewall spacers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.