High connectivity device stacking
US11257790B2 · kind B2 · utility
1Cited by
153References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2020 |
| Grant date | Feb 22, 2022 |
| Priority date | — |
| Expiry date | Mar 10, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10378
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure generally relates to stacked miniaturized electronic devices and methods of forming the same. More specifically, embodiments described herein relate to semiconductor device spacers and methods of forming the same. The semiconductor device spacers described herein may be utilized to form stacked semiconductor package assemblies, stacked PCB assemblies, and the like.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.