Compound instruction set architecture for a neural inference chip
US11263011B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 28, 2018 |
| Grant date | Mar 1, 2022 |
| Priority date | — |
| Expiry date | Mar 9, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N5/043
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device for controlling neural inference processor cores is provided, including a compound instruction set architecture. The device comprises an instruction memory, which comprises a plurality of instructions for controlling a neural inference processor core. Each of the plurality of instructions comprises a control operation. The device further comprises a program counter. The device further comprises at least one loop counter register. The device is adapted to execute the plurality of instructions. Executing the plurality of instructions comprises: reading an instruction from the instruction memory based on a value of the program counter; updating the at least one loop counter register according to the control operation of the instruction; and updating the program counter according to the control operation of the instruction and a value of the at least one loop counter register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.