Brian Taba
18Patents
2h-index
21Co-inventors
50Inventor score
Filing activity: Mar 17, 2008 → Oct 13, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10621489B2 | Massively parallel neural inference computing elements | Electricity | 23 | Active |
| US9704094B2 | Mapping of algorithms to neurosynaptic hardware | Physics | 7 | Active |
| US11521085B2 | Neural network weight distribution from a grid of memory elements | Physics | 1 | Active |
| US11501140B2 | Runtime reconfigurable neural network processor core | Physics | 1 | Active |
| US11537859B2 | Flexible precision neural inference processing unit | Physics | 1 | Active |
| US12182687B2 | Data representation for dynamic precision in neural network cores | Physics | 1 | Active |
| US11238347B2 | Data distribution in an array of neural network cores | Physics | 0 | Active |
| US11847553B2 | Parallel computational architecture with reconfigurable core-level and vector-level parallelism | Physics | 0 | Active |
| US8812413B2 | Growing simulated biological neural circuits in a simulated physical volume | Physics | 0 | Active |
| US12056598B2 | Runtime reconfigurable neural network processor core | Physics | 0 | Active |
| US12387082B2 | Scheduler for mapping neural networks onto an array of neural cores in an inference processing unit | Physics | 0 | Active |
| US12400112B2 | Efficient method for VLSI implementation of useful neural network activation functions | Physics | 0 | Active |
| US12165050B2 | Networks for distributing parameters and data to neural network compute cores | Physics | 0 | Active |
| US8165971B2 | Generating simulated neural circuits in a voxel space | Physics | 0 | Active |
| US11263011B2 | Compound instruction set architecture for a neural inference chip | Physics | 0 | Active |
| US11010662B2 | Massively parallel neural inference computing elements | Electricity | 0 | Active |
| US12067472B2 | Defect resistant designs for location-sensitive neural network processor arrays | Physics | 0 | Active |
| US11663461B2 | Instruction distribution in an array of neural network cores | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.