Integrated assemblies
US11264320B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 5, 2020 |
| Grant date | Mar 1, 2022 |
| Priority date | — |
| Expiry date | Nov 5, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some embodiments include an integrated assembly having a set of true digit-lines and a set of complementary digit-lines. Each of the complementary digit-lines is comparatively coupled with an associated one of the true digit-lines. A semiconductor substrate is under the true digit-lines. The semiconductor substrate includes semiconductor features which project upwardly from a semiconductor base and which extend along a first direction. Each of the semiconductor features has opposing sidewalls. First source/drain regions are within the semiconductor features and second source/drain regions are within the semiconductor base. The true digit-lines are coupled with the first source/drain regions. Wordlines are along the opposing sidewalls and include gating regions which gatedly couple the first source/drain regions with the second source/drain regions. Storage-elements are coupled with the second source/drain regions. In some embodiments, memory may utilize a 4F2 layout.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.