Apparatuses and methods for ordering bits in a memory device
US11269648B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 8, 2020 |
| Grant date | Mar 8, 2022 |
| Priority date | — |
| Expiry date | Oct 8, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30032
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, apparatuses, and methods for organizing bits in a memory device are described. In a number of embodiments, an apparatus can include an array of memory cells, a data interface, a multiplexer coupled between the array of memory cells and the data interface, and a controller coupled to the array of memory cells, the controller configured to cause the apparatus to latch bits associated with a row of memory cells in the array in a number of sense amplifiers in a prefetch operation and send the bits from the sense amplifiers, through a multiplexer, to a data interface, which may include or be referred to as DQs. The bits may be sent to the DQs in a particular order that may correspond to a particular matrix configuration and may thus facilitate or reduce the complexity of arithmetic operations performed on the data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.