Patent · US Active

Reusing adjacent SIMD unit for fast wide result generation

US11269651B2 · kind B2 · utility

0Cited by

8References

17Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Michael Klein · Schenefeld, DE
Nicol Hofmann · Stuttgart, DE
Cedric Lichtenau · Stuttgart, DE
Osher Yifrach · Holon, IL

Key dates

Filing date	Sep 10, 2019
Grant date	Mar 8, 2022
Priority date	—
Expiry date	Sep 10, 2039

Classification

Technology area (CPC G)Physics
CPC primaryG06F9/3875
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A system for processing instructions with extended results includes a first instruction execution unit having a first result bus for execution of processor instructions. The system further includes a second instruction execution unit having a second result bus for execution of processor instructions. The first instruction execution unit is configured to selectively send a portion of results calculated by the first instruction execution unit to the second instruction execution unit during prosecution of a processor instruction if the second instruction execution unit is not used for executing the processor instruction and if the received processor instruction produces a result having a data width greater than the width of the first result bus. The second instruction execution unit is configured to receive the portion of results calculated by the first instruction execution unit and put the received results on the second results bus.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.