Semiconductor devices and methods of forming semiconductor devices
US11270938B2 · kind B2 · utility
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1References
18Claims
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Assignee
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Key dates
| Filing date | Jun 24, 2020 |
| Grant date | Mar 8, 2022 |
| Priority date | — |
| Expiry date | Jun 24, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B61/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device may be provided, including a base layer, an insulating layer arranged over the base layer, a memory structure arranged at least partially within the insulating layer, where the memory structure may include a first electrode, a second electrode, and an intermediate element between the first electrode and the second electrode, and a resistor arranged at least partially within the insulating layer, where the resistor may be arranged in substantially a same horizontal plane with one of the first electrode and the second electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.