Phase change memory using multiple phase change layers and multiple heat conductors
US11271151B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2019 |
| Grant date | Mar 8, 2022 |
| Priority date | — |
| Expiry date | Aug 2, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C13/0097
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is presented for reducing a reset current for a phase change memory (PCM). The method includes forming a bottom electrode, constructing a PCM cell structure including a plurality of phase change memory layers and a plurality of heat transfer layers, wherein the plurality of phase change memory layers are assembled in an alternating configuration with respect to the plurality of heat transfer layers, and forming a top electrode over the PCM cell structure. The plurality of phase change memory layers are arranged perpendicular to the top and bottom electrodes. Additionally, airgaps are defined adjacent the PCM cell structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.