Method of programming memory device and related memory device having a channel-stacked structure
US11276467B2 · kind B2 · utility
1Cited by
14References
10Claims
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Key dates
| Filing date | Mar 31, 2020 |
| Grant date | Mar 15, 2022 |
| Priority date | — |
| Expiry date | Mar 31, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A vertical NAND string in a channel-stacked 3D memory device may be programmed using ISPP scheme, wherein a preparation step is introduced immediately after each verification step and before the start of a corresponding verification step. During the preparation step, the electrons accumulated in the channel may be drained by the selected bit line for enhancing the coupling effect of the channel, thereby reducing program disturb and increasing program speed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.