Gate-all-around integrated circuit structures having self-aligned source or drain undercut for varied widths

US11276691B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Biswajeet Guha · Hillsboro, US
• Jun Sung Kang · Hillsboro, US
• Bruce Beattie · Portland, US
• Stephen M. Cea · Hillsboro, US
• Tahir Ghani · Portland, US

Key dates

• Filing date: Sep 18, 2018
• Grant date: Mar 15, 2022
• Expiry date: Jul 1, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6219

Abstract

Gate-all-around integrated circuit structures having self-aligned source or drain undercut for varied widths are described. In an example, a structure includes first and second vertical arrangements of nanowires above a substrate, the nanowires of the second vertical arrangement of nanowires having a horizontal width greater than a horizontal width of the nanowires of the first vertical arrangement of nanowires. First and second gate stack portions are over the first and second vertical arrangements of nanowires, respectively. First embedded epitaxial source or drain regions are at ends of the first vertical arrangement of nanowires and extend beneath dielectric sidewalls spacers of the first gate stack portion by a first distance. Second embedded epitaxial source or drain regions are at ends of the second vertical arrangement of nanowires and extend beneath the dielectric sidewalls spacers of the second gate stack portion by a second distance substantially the same as the first distance.