Register renaming after a non-pickable scheduler queue
US11281466B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Oct 22, 2019 |
| Grant date | Mar 22, 2022 |
| Priority date | — |
| Expiry date | Oct 22, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A floating point unit includes a non-pickable scheduler queue (NSQ) that offers a load operation concurrently with a load store unit retrieving load data for an operand that is to be loaded by the load operation. The floating point unit also includes a renamer that renames architectural registers used by the load operation and allocates physical register numbers to the load operation in response to receiving the load operation from the NSQ. The floating point unit further includes a set of pickable scheduler queues that receive the load operation from the renamer and store the load operation prior to execution. A physical register file is implemented in the floating point unit and a free list is used to store physical register numbers of entries in the physical register file that are available for allocation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.